Present day high density integrated circuits require there to be a plurality of levels of metal interconnection between the various devices on a semiconductor chip. These metal interconnections include local interconnects or straps which connect together closely located devices, and also include global interconnects or metal lines which may connect together many circuits at various locations on a single chip. Generally, fabrication of metal interconnects involves deposition of a conductive layer over the devices to be connected, and etching of the conductive layer to form the interconnect between the devices. However, damaging underlying devices or structures during etching of the conductive layer has been a recurring problem during fabrication of metal interconnects.
Until recently, wet etching was widely used to pattern features, such as metal interconnects, in integrated circuits. Wet etching achieves the necessary high selectivity to underlying features for minimizing damage to these features. However, since wet etching is generally isotropic, it is very difficult to control dimensions of submicron features. Thus, reactive ion etching (RIE) is the preferred method for patterning of metal interconnects in advanced integrated circuits. RIE provides an anisotropic etch that is essential for controlling line widths of interconnects with dimensions of less than one micron. The problem with RIE is that the selectivity to underlying features is not always as high as required. This problem is accentuated as device dimensions become smaller. In this regard, as underlying layers become thinner the amount of overetching that can be tolerated is accordingly reduced.
Additionally, new circuit designs that increase device density make the problem increasingly difficult. One example is a partially covered contact. In this design, the area required by an interconnect layer is reduced by allowing the interconnects to only partially cover the contacts. Difficulties arise when the RIE overetch required to pattern the interconnect damages the contact. Thus, the yield of the device is reduced.
Several solutions to this problem, using etch stops, have been proposed. For instance, U.S. Pat. No. 4,960,489, to Roeska et al. discloses forming contacts on top of metal lines using an etch stop between the contact material and the underlying material. However, Roeska et al. requires that the underlying material be patterned along with the etch stop, i.e., the etch stop is not removed separately from the underlying material.
U.S. Pat. No. 4,925,524, to Beatty discloses using chromium as an etch stop. The chromium is removed with an O.sub.2 /Cl.sub.2 plasma with high selectivity to SiO.sub.2. However, it is known that silicon and certain other commonly used metals, such as aluminum, are etched by chlorine containing etches.
U.S. Pat. No. 4,668,335, to Mockler et al. relates to an aluminum reactive ion etching process that stops on a layer of TiW. The TiW layer is then removed with a wet etch. However, for submicron dimensions, lateral etching of the TiW by the wet etch may result in severe undercutting and undesirable lifting of the metal lines.
In the article entitled "HPSAC-A Silicided Amorphous-Silicon Contact and Interconnect Technology for VLSI", by Wong et al., IEEE Transactions on Electron Devices, vol. ED-34, No. 3, March, 1987, pages 587-591, a titanium etch stop layer is disclosed to pattern silicon lines. All of the silicon and titanium that are in contact with each other are converted to TiSi.sub.2 by annealing. The unreacted titanium is then removed by a wet etch. The Wong et al. process has good selectivity to underlying layers and also has good line width control. However, the process is limited to the formation of silicides. In this regard, silicides have a relatively high resistivity. This is disadvantageous since interconnect delays are minimized by lowering of line resistance. Additionally, for local interconnects which can tolerate some degree of high resistivity because of short line lengths, the thickness of the silicide line is limited to that which is compatible with low junction leakage.